GIREG_RX.SCLK Dynamic Default/Dynamic User-Defined Delay Block Diagram Figure 2.9. GIREG_RX.SCLK Static Default/Static User-Defined Delay Inversion Enabled Interface Figure 2.8. GIREG_RX.SCLK Bypass Inversion Enabled Interface Figure 2.7. GIREG_RX.SCLK Bypass/Static Default/Static User-Defined Delay Inversion Enabled Block Diagram Figure 2.6. GIREG_RX.SCLK Static Default/Static User-Defined Delay Interface Figure 2.5.

GIREG_RX.SCLK Bypass/Static Default/Static User-Defined Delay Block Diagram. 2 FPGA-IPUGДЈ Contents Acronyms in This Document Introduction uick Facts Features Conventions Nomenclature Signal Names Functional Description Overview Functional Diagrams GIREG_RX.SCLK GOREG_TX.SCLK Signal Description Attribute Summary IP Generation and Evaluation Licensing the IP Generation and Synthesis Running Functional Simulation Hardware Evaluation References Technical Support Assistance Revision History FPGA-IPUGД¤ Figures Figure 2.1. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice s product could create a situation where personal injury, death, severe property or environmental damage may occur. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same.

Buyer shall not rely on any data and performance specifications or parameters provided herein. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. 2 Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose.

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